An increasing number of consumer devices are equipped with wireless interfaces. The number of different wireless interfaces in a single device is rising. Cost pressure requires the implementation of multiple wireless standards e.g. in a single package or on a single chip. Analogue/RF front-end designers aim at software-reconfigurable (SRR) or software-defined radios (SDR), which share a significant amount of front-end building blocks. When shared, however, these blocks have to be adjustable and/or programmable, hence the amount of control signals increases. In addition, the usage of more advanced technology (130-nm, 90-nm, etc.) degrades the reliability of the manufactured designs. To avoid too large design margins (and the accompanying cost), digital compensation techniques are required to compensate for the analogue imperfections. Again, these techniques require more programmability and observability of the front-end; also here, more control pins (control and monitoring) are required.
Flexible front-end designs feature an increasing amount of control pins. Single standard front-ends may face more control pins since digital compensation techniques will be used. For multiple standard front-ends, flexibility requires an increase of control facilities. As a consequence, the amount of control pins is tremendously increasing.
Since current front-end designs still exhibit only a moderate amount of functionality to monitor and steer, state-of-the-art solutions for interconnect schemes essentially rely on point-to-point or bus-based topologies and plain digital solutions. These approaches however have significant disadvantages in the context of analogue/RF designs.
Point-to-point topologies essentially scale linearly with at least the number of control points in the analogue design. When implemented digitally, they also scale linearly with the number of control bits per control point. This introduces a significant routing overhead and design and verification cost. Three major issues arise with current state-of-the-art solutions.
The first issue relates to point-to-point routing of the control pins to each analogue block on the chip. The main disadvantage of such approach is missing scalability. Adding control bits requires a change in the floorplanning, routing, connections per module, and possibly even in the I/O pads of the chip.
Secondly, digital Network-on-Chip (NoC) solutions (layer 3) are too complicated. Digital bus solutions (layer 2) usually require parallel busses and do not take into account crosstalk requirements on analogue/RF chips. Bus-based solutions come with a large overhead in routing area and control logic. Moreover, parallel busses have a higher cross-talk potential and are harder to shield than a single bit line. Moreover, bus protocols are not necessarily made for the specific requirements in a front-end context (slow vs. fast, short vs. long instruction words, broadcast/multi-cast to different receiving nodes).
Thirdly, the usage of plain digital signalling may be considered. A better choice is the usage of e.g. differential and low-voltage signalling (e.g. Low Voltage Differential Signalling (LVDS)).
Hence, flexible front-ends are important in the context of reactive, software-reconfigurable, software-defined or cognitive radios. A particularly useful feature is controllability and observability of all front-end resources in order to guarantee reliable, energy-efficient, and quality-aware operation.
Patent application EP1351403-A2 relates to a transceiver with front-end reconfiguration. The described interconnect scheme facilitates the access of an essentially digital controller to the resources on an analogue/RF chip for both steering and monitoring purposes.
The present disclosure aims to provide a front-end design with improved controllability and observability capabilities.